A Design Verification Engineer Blog
I’m a design verification engineer and this is where I keep my notes, my thoughts, my experiences or anything interesting that I think should belong here. :D
Who am I
I’m a design verification engineer and I’ve been in this industry for quite a while. Mostly this dvtalk blog is for keeping notes of what I know, and also problems big and small which I faced. My main task is verification so I work with systemverilog, uvm everyday and these are what I know the most. However, now and then, I also find myself struggling with formal verification, STA timing, design, and also scripting. Talking about scripting, I have been using csh and perl for a long time before switching to zsh and python recently. And also I love vim, gosh, it is the best.
What you’ll find here
- You’ll find my randoms. Let’s just say my randoms are just a bit better organized piece of my notes since I note a lot. This will be where I keep them. They will be about systemverilog or uvm or vim. Just some random interesting things that I really don’t now where to post.
- You’ll find my how to. These will be guides to do specific things. Mostly they will be about systemverilog and uvm and vim also, I guess. (Just keep it like that, since at this very moment I have nothing in this category =D ).
- And you’ll also find my thoughts.
OK, that’s it mates. Use the search box if you need anything. And if you cannot find what you need, well, later then. :D
Posts:
- Example Usage of Interface Class in Systemverilog
- Systemverilog Streaming Operator Example
- Using Plusargs in UVM Test
- Systemverilog Enum For Better Code Abstraction
- uvm_pool example with Systemverilog semaphore
- How to use uvm_barrier and uvm_barrier_pool
- How to use uvm_event and uvm_event_pool
- How uvm factory actually works
- How to use uvm factory
- Singleton class in Systemverilog
- DPI example with AES-Openssl C-model
- Summarize - virtual in Systemverilog
- Systemverilog OOP - Polymorphism
- Systemverilog macro with examples
- About Systemverilog process and fork join
- Forcing Signals with Questasim/ModelSim
- Using Vim terminal
- Differences between uvm test and uvm testbench top
- Install tmux without root and Internet access
- std::randomize examples
- My EDAPlayground
- Choosing grandparent class