Forcing Signals with Questasim/ModelSim
I’ve been using vcs and questasim for verification for a while, and both of these tools allow us to interact with the simulator using their cli. We can use them for debugging, create checking point, restore simulation, … . But mostly for my case, I use this cli for forcing signals. And this method help me in many situations such as creating some error cases (for testing purpose), or forcing signals from the logic that has not been implements yet. Let’s go through some examples for forcing signals using Questasim (or another version of this eda tool is ModelSim).
How to force signals
As mentioned, we force signals using the interactive mode of those EDA tool, so whenever we in the command line interface (aka cli) we can call the force commands to force signals. Usually, I create a file containing forcing commands, then source this file during simulation like below.
For Questasim and VCS, these commands is the Tcl-based command, which means you will use tcl syntax for writing your force file.
Some examples of forcing signals using Questasim
First up
- Make sure your signals have correct path, you can find signal path by using Questasim cli command in cli mode:
find nets -recursive -ports /top/*TOP*/*MODULE_A*/*RESET*
- Check your tcl syntax carefully.
- Careful with radix format. Tcl will understand this radix format
0b11
, but for Questasim, we need to write data value with this format:'b11
,'hfaab
,'d1024
. So check the EDA user guide carefully. - If you use force file like this:
vsim -do <force_file.tcl>
, considering using below template
Forcing Examples
Description | Code |
---|---|
forcing signals with fix value from certain simulation time | This means: From 1000ns of simulation time, I_SIGNAL_A[1:0] will be 2'b11, I_SIGNAL_B will be 1'b1 |
forcing signal to be similar to other signal | This means: From 1000ns of simulation time, at every event of I_CLK (rising edge, falling edge), get the value of I_CLK (using examine command), and force the I_SIGNAL_C with that value |
forcing signal when another signal got x value | This means: From 1000ns of simulation time, when I_SIGNAL_A change to X value, force the I_SIGNAL_C to be 0 |
forcing signal to be a clock | This means: When I_RESET_N changes value and the I_RESET_N has 1'b1 value, force the I_CLK_B to be 1, after 0.5ns force the I_CLK_B to be 0. After 1ns from the moment I_CLK_B first forced to be 1, repeat the same sequence. Then we'll has I_CLK_B forced as a clock with 1ns clock cycle. |
forcing signal when another signal active 1 the first time | This means: When I_SIGNAL_E change value to 1 the first time, force the I_SIGNAL_D to 1. |
Finding more information
Read the User Manual released by Questasim for more information and example on how to force signals. The manual files usually can be found at the installation directory of each tool. Besides, you could also refer the ModelSim PE manual. It’s a free download tool from Mentor for education purpose and the commands are similar to Questasim.
[Tags
linux_env
eda_tool
]